The present invention relates to a method for producing an integrated circuit, and more particularly to a method for producing very thin semiconductor chips comprising an integrated circuit. Chips according to the invention may have a thickness of significantly less than 100 μm, advantageously they have a thickness of approximately 50 μm or less, and even more preferably a thickness of approximately 20 μm. Such thin chips are well suited for producing so-called 3D chips in which a plurality of thin chips each comprising an integrated circuit are stacked one on top of another. Furthermore, such thin chips have a certain flexibility as a result of the small material thickness, such that they can be used on flexible carrier materials, such as for example a plastic film.
One possible approach for producing such thin chips comprising an integrated circuit may involve producing the integrated circuit on a semiconductor wafer having a thickness of for example 500 μm up to 800 μm. After the integrated circuit has been produced, the rear side of the semiconductor wafer is eroded by a mechanical and/or chemical process. The semiconductor wafer, which typically carries a plurality of integrated circuits, then has to be divided in order to form the chips. This is conventionally done by sawing, separation by grinding, cutting or scribing and breaking. One method for dividing semiconductor wafers to form chips is described in DE 40 29 973 A1.
This approach has the disadvantage that a considerable part of the wafer material is lost as a result of the erosion. Furthermore, it is necessary to provide relatively large distances between the individual chips on a wafer in order that there is enough space available for sawing, separation by grinding, etc. Typical distances are in this case of an order of magnitude of 150 μm. All this has a disadvantageous effect on the costs for the production of thin integrated circuits, i.e chips having material thicknesses of less than 150 μm.
WO 2005/104223 A1 describes a method wherein a plurality of vertical trenches are produced at the first surface of the semiconductor wafer by means of an anisotropic etching process. Afterward, the opened first surface is closed off again by means of an epitaxial layer and the semiconductor wafer is subjected to a thermal treatment (annealing). The intention is here to form individual closed channels below the first surface. Vertical entrances to the concealed channels are then produced in a further anisotropic etching process. The inner walls of the channels and of the vertical entrances are subsequently provided with an oxide layer by means of an oxidation process. The channels and vertical entrances surround a wafer section at the first surface, in which section a circuit structure is then produced in a conventional manner. Afterward, the oxide layer is removed in the channels and vertical entrances by means of a further etching process, such that the wafer section is connected to the rest of the wafer only via web-like connections on its underside. These connections are broken by tearing out the wafer section upward from the remaining semiconductor wafer, wherein a torsional movement is also proposed. This method is intended to enable the production of chips having a thickness of less than 10 μm.
In this known method, producing the deeply situated oxide layers below the wafer section and selectively etching them out later seem very complicated and difficult. Moreover, this method has the disadvantage that the formation of the web-like connections is highly dependent on individual process parameters which can vary in manifold ways. Therefore, the formation of web-like connections having exactly defined properties is extremely difficult, if not impossible. If the web-like connections turn out to be too thick, there is a considerable risk of the chip being damaged in the course of being released. If they turn out to be too thin, the necessary stability for the production of the circuit structure is lacking. The reproducibility of the web-like connections and the process reliability can therefore be ensured only with very high outlay, if at all.
A paper by Overstolz et al. entitled “A Clean Wafer-Scale Chip-Release Process without Dicing Based on Vapor Phase Etching”, 17th IEEE International Conference on Micro Electro Mechanical Systems, January 2004, pages 717 to 720, discloses releasing a micromechanical sensor, namely an inclinometer, from a silicon material solely by means of various etching processes. In this case, an SOI wafer (Silicon on Insulator) serves as the starting material. In order to release the inclination sensor, trenches and holes are etched both from the front side and from the rear side of the wafer material. In addition, the oxide layer lying in the semiconductor material is partially etched out by introducing hydrofluoric acid vapour through the holes at the front side and rear side into the interior of the semiconductor wafer.
U.S. Pat. No. 6,165,813 describes a method for releasing thin chips fixed to a flexible substrate by bending the substrate. U.S. Pat. No. 6,521,068 describes a method for separating chips from a substrate, wherein a region below the chip is heated by a laser.
JP 2002-299500 describes the removal of chips by means of a so-called dummy substrate.
Finally, production and use of porous silicon is known in the art. DE 197 52 208 A1 discloses a method for producing a membrane sensor, wherein a thin layer of silicon carbide or silicon nitrite is deposited over a region of porous silicon. The porous silicon is subsequently removed as sacrificial material using ammonia. As a result, a cavity arises below the membrane layer of silicon carbide or silicon nitrite, which cavity thermally decouples the sensor membrane from the remaining substrate.
A method for producing a piezoresistive pressure sensor with a freely suspended membrane composed of monocrystalline silicon is described in a publication by Armbruster et al., “Surface Micromachining of Monocrystalline Silicon Membranes Using a Silicon Micro Grid of Sintered Porous Silicon”, Technical Digest of Eurosensors XVIII, Rome, Sep. 12 to 15, 2004, pages 22/23. In this method, in a first step a p-doped silicon substrate is provided with shallow n-doped regions and with deep n+-doped regions. The shallow n-doped regions form a lattice structure at the surface of the p-doped silicon substrate. The p-doped silicon substrate below the lattice structure is subsequently converted into porous silicon. For this purpose, the regions of the p-doped substrate below the n-doped lattice regions are undercut in concentrated hydrofluoric acid. A subsequent sintering process has the effect that the sintered porous silicon forms a cavity below the lattice structure. An epitaxial layer is subsequently applied above the lattice structure, said epitaxial layer forming the sensor membrane of the pressure sensor. The cavity formed by means of the porous silicon is closed off again in this way.
Furthermore, porous silicon is used in the so-called ELTRAN process (Epitaxial Layer TRANsfer), which can be used to produce SOI wafers. The procedure is described in a publication by T. Yonehara and K. Sakaguchi that appeared in JSAP International No. 4, July 2001, entitled “ELTRAN; Novel SOI-Wafer Technology”.